The present invention relates generally to integrated circuits, and more specifically to switches that are capable of being programmed.
A programmable switch typically utilizes wide multiplexers consisting of n-channel pass gates in which the gate voltage of the selected path is referenced to the same power supply as the logic gates that drive the inputs and sense the outputs. The wide multiplexer circuits are used to program route connections within a programmable logic device (PLD). To minimize die area, n-channel pass gates are used as the switching elements to select a desired data signal path on which a data signal is passed. A programmable circuit such as a latch or an electrically erasable link drives the pass transistor gate voltage. The voltage provided at the gate of the pass transistor in the selected path is typically the same voltage as the power supply to the logic gates in the circuit. Since the n-channel pass transistor conduction turns off when the output reaches the power supply voltage less the threshold voltage (VPWRxe2x88x92VT), a p-channel transistor configured as a half-latch is typically used to restore the signal level to a full swing. However, such a circuit configuration is slow, particularly for the rising edge, which is a result of the transistor conductance decreasing as the output voltage rises. Since the n-channel pass transistor gate voltage is at VPWR, the circuit can drive the voltage only to VPWRxe2x88x92VT. The speed of such a circuit is limited by the channel conductance of the pass transistor, which reduces as the output voltage increases. As the total switching activity of the circuit increases, the load on the power supply increases which reduces the power supply voltage and increases the circuit delay.
A programmable switch circuit is constructed with pass transistors wherein the gate of the selected path thereof is driven to a higher voltage. The higher voltage is achieved by distributing a xe2x80x9cquietxe2x80x9d supply voltage that is not loaded with circuits that switch during normal operation. In this manner, the gate voltage is driven to nearly the largest value that the process can reliably allow. The gate voltage will not reduce as total switching load of the chip increases. One advantage provided by such a circuit configuration in accordance with the present invention is reduction in propagation delay resulting from an increase in the average conductance of the n-channel pass transistor and increasing the range in which the output voltage is driven, which in one embodiment is VPWR+less VT.